This invention relates to integrated circuit memory devices and more particularly to circuits and methods for testing memory cell arrays of integrated circuit memory devices.
Integrated circuit memory devices are widely used in consumer and commercial electronics. As the integration density of these devices continues to increase, the number of cells in a memory cell array may continue to increase. With the increased number of memory cells, it may become increasingly difficult to test the memory cell array.
As is well known to those of skill in the art, a memory cell array generally includes a plurality of data line outputs. In a normal, non-test mode, the data on the data line outputs is transmitted to global output lines. In contrast, in a parallel bit test mode in which a plurality of data bits are concurrently output for comparison testing, a separate parallel bit test circuit may be used. In a conventional parallel bit test circuit, a plurality of data units controlled by one column select line are output through a sense amplifier. The output data is selected in groups of two to be compared in a primary comparison. The compared data in the primary comparison is again selected in groups of two to be compared in a secondary comparison, and the compared data in the secondary comparison are again selected in groups of two to be compared in a tertiary comparison. Thus, the comparison operation may be extended. Separate output drivers may be provided for each of the compared data units. Signals output by each of the output drivers may be transmitted to an output multiplexer.
Referring now to FIG. 7, conventional parallel bit test circuits and methods include normal drivers 701, 703, 705, 707, 709, 711, 713 and 715. In a memory cell array 760, eight data units are amplified by corresponding sense amplifiers to become data line outputs TD00/TD0BO, TD01/TD0B1, TD02/TD0B2, TD03/TD0B3, TD04/TD0B4, TD05/TD0B5, TD06/TD0B6 and TD07/TD0B7. The normal drivers 701, 703, 705, 707, 709, 711, 713 and 715, in a normal output mode, respectively transmit the corresponding data line outputs TD00, TD01, TD02, TD03, TD04, TD05, TD06 and TD07 to global output lines FDI00, FDI01, FDI02, FDI03, FDI04, FDI05, FDI06 and FDI07. In the parallel bit test mode, data of the data line outputs TD00, TD01, TD02, TD03, TD04, TD0S, TD06 and TD07 is compared in response to a selection signal that indicates a selected number of compared bits and outputs the compared signals. The test drivers 761, 763, 765, 767, 769, 771 and 773 receive corresponding output signals of the data comparison.
The parallel bit test circuit includes primary comparators 727, 729, 731 and 733, primary switches 735, 737, 739 and 741, secondary comparators 743 and 745, secondary switches 747 and 749, a tertiary comparator 751 and a tertiary switch 759. The primary comparator 727 compares TD00 to TD01 to output the primary compared signal FCOO. The primary comparator 729 compares TD02 to TD03 to output the primary compared signal FC01. The primary comparator 731 compares TD04 to TD05 to output the primary compared signal FC02. The primary comparator 733 compares TD06 to TD07 to output the primary compared signal FC03. Also, in the primary parallel test mode, the primary switch 735 receives FC00 to output FC00 to an input terminal of the test driver 761. In the primary parallel test mode, the second switch 737 receives FC01 to output FC01 to an input terminal of the test driver 763. In the primary parallel test mode, the primary switch 739 receives FC02 to output FC02 to an input terminal of the test driver 765. In the primary parallel test mode, the primary switch 741 receives FC03 to output FC03 to an input terminal of the test driver 767.
The secondary comparator 743 compares FC00 to FC01 to output a secondary compared signal SC00. The secondary comparator 745 compares FC02 to FC03 to output a secondary compared signal SC01. In the secondary parallel test mode, the secondary switch 747 receives SC00 to output SC00 to an input terminal of the test driver 769. In the secondary parallel test mode, the secondary switch 749 receives SC01 to output SC0L to an input terminal of the test driver 771.
The tertiary comparator 751 compares SC00 to SC0L to output a tertiary compared signal TC0. In the tertiary parallel test mode, the tertiary switch 759 receives TC0 to output TC0 to an input terminal of the test driver 773.
Since the distance between a sense amplifier and a multiplexer may vary based on the internal layout of the integrated circuit, the size of the drivers 761, 763, 765, 767, 769, 771 and 773 that drive some of the multiplexers may need to increase. Moreover, the number of output drivers may depend on the number of comparisons.
Accordingly, conventional parallel bit test circuits and methods may consume an excessive area in an integrated circuit memory device. Moreover, since the number and/or size of drivers connected to the data output lines may vary, a difference in speed between input and output data in normal mode may be produced.
It is therefore an object of the present invention to provide improved circuits and methods for testing integrated circuit memory devices.
It is another object of the present invention to provide integrated circuit memory device testing circuits and methods that need not unduly increase the integrated circuit area that is occupied by test circuitry.
It is still another object of the present invention to provide integrated circuit memory testing circuits and methods that can reduce the speed differences between input and output data in normal mode.
These and other objects are provided according to the present invention by integrated circuit memory device testing circuits and methods that compare data on a selected number of the data line outputs of a memory cell array to one another to produce comparison results, in response to a selection signal that indicates the selected number of the data line outputs to be compared to one another. A shared test driver is responsive to the comparison circuit to provide the comparison results to an associated global output line for at least two values of the selection signal that indicate at least two selected numbers of data line inputs to be compared to one another. By sharing test drivers, separate test drivers need not be provided for each selected number of the data line outputs that are compared to one another. The number of test drivers may therefore be reduced so that the area occupied by the testing circuits may be reduced.
More specifically, circuits and methods for testing data on data line outputs of a memory cell array includes a plurality of normal drivers that transmit the data on the data line outputs to global output lines in a normal output mode. Comparison circuits and methods compare the data on a selected number of the data line outputs to one another to produce comparison results, in response to a selection signal that indicates the selected number of the data line outputs to be compared to one another, in a parallel bit test mode. The normal drivers preferably do not transmit the data on the data line outputs to the global output lines in the parallel bit test mode.
A plurality of shared test drivers are responsive to the comparison circuit to provide the comparison results to at least one of the global output lines for at least two values of the selection signal. Preferably at least one of the test drivers is responsive to the comparison circuit to provide the comparison results to an associated global output line for at least two values of the selection signal that indicate at least two selected numbers of data line inputs to be compared to one another. Accordingly, the number of test drivers need not be unduly increased and speed differences between input and output data in normal mode need not be produced. Differences in output speeds between output data on different global output lines may also be reduced.
Comparison circuits according to the invention preferably comprise a plurality of primary comparators, each of which compares the data on a first selected number of the data line outputs to one another to produce primary comparison results. A plurality of secondary comparators compare the primary comparison results to one another to produce secondary comparison results. At least one tertiary comparator compares the secondary comparison results to one another to produce tertiary comparison results. The primary comparators may operate in response to a selection signal that indicates a first selected number of the data line outputs are to be compared to one another in the parallel bit test mode. The secondary comparators may operate in response to a selection signal that indicates that a second selected number of the data line outputs that is greater than the first selected number are to be compared to one another in the parallel bit test mode. The tertiary comparator may operate in response to a selection signal that indicates that an even greater number of data line outputs are to be compared to one another in the parallel bit test mode. Accordingly, the area occupied by the parallel bit testing circuits in the integrated circuits need not be increased unduly. The speed differences between input and output of the data in normal mode can be reduced, and the difference in output speeds between output data can be reduced.